Method for producing a semiconductor component and a semiconductor component, especially a membrane sensor

ABSTRACT

In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that is different from that of the cavity. This permits different pore sizes and/or porosities to be produced, which is used in producing the cavity for improved etching gas transport. Also, mesopores may be produced in the diaphragm region and nanopores may be produced as an auxiliary structure in what is to become the cavity region.

FIELD OF THE INVENTION

[0001] The present invention relates to a method for manufacturing asemiconductor component.

BACKGROUND INFORMATION

[0002] Semiconductor components, in particular diaphragm sensors, andmethods for manufacturing diaphragm sensors on the basis of asemiconductor substrate, e.g., a silicon wafer, on which a flat, porousdiaphragm region is situated as a support layer for sensor structuresand which has a cavity under the diaphragm region for in particularthermal insulation of the diaphragm, are already known.

[0003] Most diaphragm sensors presently existing in the market areusually implemented as thin-film diaphragm sensors. For this purpose,layer systems are deposited on a substrate in thicknesses between a fewtens of a nm and a few μm, and subsequently the substrate is removed inpredefined regions to obtain unsupported diaphragm regions. Sensorstructure elements can then be placed in the center of the diaphragm.

[0004] Another option for exposing the diaphragm is by use of surfacemicromechanics (SMM), in which a sacrificial layer is normally used,which is applied to the front of a carrier substrate before depositingthe diaphragm. The sacrificial layer is later removed from the front ofthe sensor through “dissolution openings” in the diaphragm, whereby anunsupported structure is obtained. These surface micromechanical methodsare relatively complicated due to the need for separate sacrificiallayers.

[0005] German Patent Application No. DE 100 325 79.3 describes a methodfor manufacturing a semiconductor component and a semiconductorcomponent manufactured by this method, in which a layer of poroussemiconductor material is placed over a cavity for a diaphragm sensor inparticular.

[0006] Using these measures, it is possible to considerably simplify thedesign of an SMM semiconductor component, because no sacrificial layerneeds to be additionally applied, and the diaphragm itself or asubstantial part thereof is produced from semiconductor material.

[0007] However, tests have shown that a porous diaphragm may be damagedas early as during manufacturing, and even under conventional conditionsof use damage cannot always be reliably prevented.

SUMMARY

[0008] An object of the present invention is to prevent damage to thediaphragm during manufacture or under normal conditions of use.

[0009] The present invention is generally directed to a method formanufacturing a semiconductor component, a diaphragm sensor having asemiconductor substrate in particular, in which a porous diaphragm layerand a cavity underneath the porous diaphragm layer are produced to formunsupported structures for the component. In accordance with the presentinvention, in the region of the porous diaphragm layer the semiconductorsubstrate has a doping that is different from that of the region of whatis to become the cavity, the semiconductor material of the diaphragmlayer is made porous, and the semiconductor material underneath theporous semiconductor material is removed or partially removed andrearranged to form a cavity. This procedure may have the advantage thatthe properties of the porous diaphragm layer and the production of thecavity may be tuned to one another in such a way that, for example, whenthe cavity is etched, the gas thus generated is able to escapeunhindered through the porous diaphragm layer, or an auxiliary structurehaving an appropriate pore size which is different from the pore size inthe diaphragm layer is initially created in the region of the cavity,always with the objective to prevent damage to the porous diaphragmlayer at the time the cavity is produced.

[0010] This precursor or auxiliary structure may then be removed or, forexample, rearranged in a high-temperature process in a further step.

[0011] In a further preferred embodiment of the present invention, inthe region of the porous diaphragm layer, the semiconductor materialsubstrate receives doping which varies in the lateral and/or verticaldirection. Different types and degrees of doping result in pores ofdifferent sizes and/or different types when porous semiconductors, forexample, porous silicon, are manufactured, where an electrochemicalreaction between hydrofluoric acid and silicon, with the siliconsemiconductor substrate (e.g., silicon wafer) functioning as an anodewith respect to a hydrofluoric acid electrolyte and the semiconductorsubstrate being additionally illuminated (for n-doped semiconductorregions), is normally used. Thus, according to the present invention,larger pores and/or pores with a higher degree of porosity are producedin the lateral and/or vertical direction in certain diaphragm regions,the gas produced in etching the cavity being able to escape more easilythrough these pores. In this way, damage to the sensitive porousdiaphragm layer by bubble formation during etching of the cavity isprevented. In conventional porous diaphragm structures the pores areoften unable to ensure controlled, sufficient escape of the gas from thecavity during etching, which in the worst case may ultimately result indamage to the diaphragm.

[0012] In a particularly preferred embodiment of the present invention,the doping of the semiconductor material for the edge region and centralregion of the diaphragm is selected in such a way that mesopores (poreson the order of 5 nm to 50 nm) are formed in the edge region andmacropores (pores greater than 50 nm and up to a few μm) or mesopores ornanopores having a higher porosity compared to the edge region areformed in the central region of the diaphragm. In the edge region of thediaphragm having a lower porosity, a good layer quality is possible, forexample, for a subsequent epitaxial process, while in the central regionof the diaphragm the epitaxial quality is comparatively lower due tohigher-porosity sections. In many applications, as an SMM pressuresensor, for example, this is, however, unimportant, because theproperties of the pressure sensor are not impaired thereby.

[0013] For example, the central region of the diaphragm obtained from asilicon wafer receives an n-type doping to produce macropores, while theedge region of the diaphragm is provided with p⁺ doping to obtainmesoporous silicon.

[0014] In a further, particularly advantageous embodiment of the presentinvention, the semiconductor substrate is doped differently in theregion of the diaphragm layer and in the region of what is to become thecavity in such a way that mesopores may be produced in the semiconductormaterial of the diaphragm layer and nanopores (pores from 2 nm to 5 nm)having a comparatively higher porosity may be produced as a “precursorstructure” in the cavity region, and in a further step the nanoporousprecursor structure is removed. The production of a small-pore precursorstructure prevents the formation of comparatively large air bubbles,which makes it possible to adequately remove the gas bubbles through theporous diaphragm layer. In this procedure, use is made of the fact thatthe “nanostructure” has a considerably higher internal surface area thanthe “mesostructure” of the diaphragm region, which is usable in asubsequent process step for a shorter oxidation time. This makes itpossible to subsequently produce a completely oxidized nanostructurewhich is then selectively removable in a subsequent etching process,e.g., in a vapor etching process. A vapor etching process, inparticular, additionally suppresses problems at the time of drying thediaphragm such as adhesion of the porous layer to the substrate bottomdue to vertical capillary forces which frequently occurs at the time ofdrying the possibly porous silicon diaphragm, which may make the porousdiaphragm layer unusable. The cavity may also be produced by rearrangingthe nanoporous layer in a high-temperature process. The mesopores of theporous diaphragm layer may be achieved, for example, from a p⁺-typedoping in a silicon wafer (specific resistivity approximately 0.02 Ωcm)at a porosity of approximately 10% to 30%, a layer thickness of 0.1 μmto 10 μm or more, using, for example, a current density of approximately1 to 20 mA/cm² in a relatively concentrated hydrofluoric acid having anHF concentration of approximately 30% to 40%. The nanoporous precursorstructure is preferably produced on the basis of a p-doped layer(specific resistivity 1 Ωcm to 10 Ωcm) in an HF concentration ofapproximately 15% to 40% and at a current density of 10 to 80 mA/cm².Using these parameters, a porosity of over 80% may be achieved over alayer thickness of 1 μm to 10 μm.

[0015] An alternative procedure in forming the cavity structure may alsoinvolve directly dissolving the semiconductor material underneath theporous layer using electrolytic polishing, for example, at comparativelyhigher current densities and lower HF concentrations. For a siliconwafer this may be achieved, for example, by p⁺-doping a starting layerto form the porous layer over the cavity and the region of what is tobecome the cavity receiving only a p-type doping. For example, thestarting layer to form the porous layer over the cavity has a p⁺-typedoping and a specific resistivity of approximately 0.02 Ωcm. At an HFconcentration of 30% to 40%, for example, and a current density ofapproximately 1 to 20 mA/m², a porosity of 10% to 30% may be achieved.The layer thickness of the porous layer may be 1 μm to 10 μm or evenmore.

[0016] In a further exemplary embodiment, in which the diaphragm regionis doped differently from what is to become the cavity region, thestarting layer receives an n-type doping having a specific resistivityof 0.1 Ωcm to 10 Ωcm, for example, to form the porous layer over thecavity. At a current density of 5 mA/cm² and a relatively low HFconcentration of 2% to 10%, macropores are preferably formed over alayer thickness of 1 μm to 10 μm, for example. The macropores have theadvantage that gases may escape through them more easily as the cavityis produced, which counteracts the porous layer being affected or evendestroyed.

[0017] The cavity region is p-doped, for example, so that a specificresistivity of 1 Ωcm to 10 Ωcm is obtained. For this case, the cavitylayer may be produced directly by electrolytic polishing at an HFconcentration of 2% to 10% and a current density of preferably greaterthan 50 mA/cm². The cavity may, however, also be produced via a“precursor structure” by producing nanopores. The “nanostructure” isobtained, for example, at an HF concentration of 15% to 40%, a currentdensity of 2 to 50 mA/cm², and preferably has a porosity greater than80%.

[0018] The layer thicknesses of the porous layer over the cavity and thecavity layer may be 1 μm to 10 μm or more, depending on the desiredapplication. Instead of the p-type doping for the cavity layer, it mayalso have p⁺- or p⁻-type doping, whereby electrolytic polishing may beperformed to immediately produce the cavity preferably at an HFconcentration of 2% to 10% and a current density of greater than 50mA/cm². Also in this case a “precursor structure” and additionalprocesses may result in the desired cavity.

[0019] The advantages of a diaphragm containing macropores may also beachieved in an embodiment in which both the diaphragm layer and what isto become the cavity region have the same doping, for example, an n-typedoping, but etching parameters other than those for the porous diaphragmare used for treating what is to become the cavity region, so that thecavity underneath the diaphragm region may be produced directly byelectrolytic polishing. For example, a starting layer for the diaphragmlayer is n-doped, so that a specific resistivity of 0.1 Ωcm to 10 Ωcm isobtained. What is to become the cavity region is doped in the same way.Subsequently macropores are produced in the starting layer over a layerthickness of 1 μm to 10 μm or more at a current density>5 mA/cm², forexample, and an HF concentration of 5% to 10%, for example, withsubstrate backlighting.

[0020] The cavity layer is then directly produced by electrolyticpolishing, which is possible using a current density that is greaterthan the current density for producing the porous cover layer.

[0021] For better control and adjustment of the current density inetching the semiconductor substrate for producing the porous diaphragmlayer over the cavity or for better adjustment of the current density inetching the semiconductor material substrate during an electrolyticpolishing process for directly producing the cavity or for producing aporous layer in the region of what is to become the cavity as a“precursor structure,” the back of the semiconductor substrate, forexample, the back of a silicon wafer is preferably illuminated.

[0022] It is also possible to produce the porous layer over the cavityusing the same doping over both regions, for example, a p⁺-type dopinghaving a specific resistivity of 0.02 Ωcm. For the starting layer, i.e.,the porous diaphragm layer over the cavity, the aim is a porosity of 10%to 30% at a comparatively high HF concentration of 30% to 40% and acurrent density of 1 to 20 mA/cm², for example. Subsequently the cavityregion may be produced directly by electrolytic polishing, for example,at an HF concentration of 2% to 10% and a current density greater than50 mA/cm², for example, or via a precursor structure to be removedlater. To form the precursor structure for p⁺-type doping, an HFconcentration of 5% to 20%, a current density of 2 to 50 mA/cm² isselected, for example, to achieve a porosity greater than 80%.

[0023] It is, however, also possible to set the HF concentrationrelatively high, as for producing the starting layer, which however, inorder to achieve a high porosity of 80%, requires a current density thatis higher than the current density for producing the starting layer.

[0024] Both the starting layer (porous diaphragm layer) and the cavitylayer may have a thickness of 0.1 μm to 10 μm or greater, as accordingto specification.

[0025] For all the above-named processes, n-doped silicon may be used asmasking for defining the diaphragm region for the case of a siliconwafer. Such a masking layer is also easily attacked when manufacturingporous silicon; therefore, it may be produced via an insulating layer,for example, of silicon nitride (Si₃N₄), in a low-pressure chemicalvapor deposition (LPCVD) process, thereby protecting the n-doped maskinglayer against electrochemical attack. An undamaged n-doped masking layeris advantageous when an epitaxial layer is to be grown on it in asubsequent process. In the case of the use of the structure as adiaphragm sensor, however, an attack of the n-doped masking regions mayoften be tolerated.

[0026] Instead of the silicon nitride layer, other layers may also beused as protective layers, for example, a conductive metal layer ofchromium/gold of an appropriate thickness.

[0027] The depth homogeneity of the laterally adjacent regions may alsobe improved by additional masking, which is of considerable advantagewhen producing macropores in particular.

[0028] Furthermore, the present invention is directed to a semiconductorcomponent, a diaphragm sensor in particular, having a substrate made ofsemiconductor material, which has a diaphragm and a cavity locatedunderneath the diaphragm for forming semiconductor component structures,the diaphragm including a layer of porous and optionally post-treated,for example oxidized, semiconductor material. An aspect of the presentinvention is that the degree of porosity of the layer deliberatelyvaries in the lateral and/or vertical direction. This makes it possible,as described above for the gases produced in etching to escape moreeasily through regions of the porous layer, which have a comparativelyhigher porosity, when producing the cavity, in particular in the case ofa difference in porosities in the lateral direction.

[0029] The porosity of the layer in the edge region of the diaphragm ispreferably lower than in the central region of the diaphragm. Thisfavors the escape of gas in the center of the diaphragm.

[0030] It is possible to regulate the escape of gas not only via thedegree of porosity, but also via the pore size. The gas permeability ofthe porous layer is increased for the same porosity but larger pores.

[0031] To favor improved gas permeability in the center of the diaphragmregion, the pore size in that area is greater than in the edge region ofthe diaphragm.

[0032] The porous layer is advantageously mesoporous in the diaphragmedge region and macroporous in the central region.

[0033] In accordance with an embodiment of the present invention, thediaphragm layer made of porous material has macropores throughout. Thepores having larger dimensions improve the possibility of gas transportas a cavity is produced. For example, the diaphragm region and theregion to become the cavity is made of, for example, n-doped silicon.The porous layer of the diaphragm region is produced, for example, usinga current density greater than 5 mA/cm² in a comparatively lowhydrofluoric acid concentration of 2% to 10% to form macropores. Toproduce the cavity, the current density is then increased, which resultsin an increase in the pore size and thus erosion of the starting layerforming the porous diaphragm layer. The result is a cavity which iscovered by a macroporous layer (pores in the range of 100 nm to a fewμm).

[0034] Furthermore, according to the present invention, a semiconductorcomponent has one or more regions of non-porous semiconductor material,whose thickness is greater than the thickness of the porous layer, arelocated within the porous layer over the cavity. Using this measure,several advantages are achieved. First, adhesion of the porous diaphragmlayer to the cavity bottom due to capillary forces during the process ofmanufacturing the porous diaphragm layer may be prevented. In the caseof an application, for example, as a pressure sensor, such a designcreates an overload protection. Not only is the adhesion of the layer tothe cavity bottom then prevented, but also the deformation of the porouslayer due to contact with the cavity bottom and any break-off ofmaterial from the porous layer. The broken-off material could block thedeflection of the diaphragm. In addition, the non-porous regions mayhave a kind of stabilizing effect on the porous layer, in particularwhen the cavity is being produced, in particular when the non-porousregions form a grid in the porous layer. Such a design also increasesthe mechanical stability of the porous layer for subsequent processsteps such as an epitaxy step.

[0035] In a preferred embodiment of the present invention, the regionshave an insular design, i.e., with no connection to the edge of thediaphragm. For example, the non-porous regions include an annularstructure. Such a structure also reduces the risk of diaphragm rupturein the region of attachment during use, for example, in the event ofoverload in that, if it is appropriately spaced from the diaphragm edge,the annular structure is supported on the cavity bottom and alleviatesthe load on the diaphragm in the area where it is attached.

[0036] Damage to the diaphragm when the cavity is being produced mayalso be counteracted if the edge region in the porous diaphragm layerincludes a non-porous region of semiconductor material, which preferablycompletely surrounds the diaphragm layer and which, by using appropriatedoping, is used as a masking layer in the manufacture of the poroussemiconductor material, i.e., when forming the cavity, and has athickness that is greater than the thickness of the porous diaphragmlayer, including the depth of the cavity. Using these measures,excellent process control is achieved, in particular in forming thecavity, whose lateral dimension changes little over its depth. This alsohelps prevent damage to the porous diaphragm layer, since uncontrolledetching in the lateral direction is prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037]FIG. 1 shows a schematic section of a silicon substrate having anSMM diaphragm.

[0038]FIG. 2 shows another embodiment of an SMM diaphragm structure.

[0039]FIGS. 3a and 3 b show schematic sections corresponding to FIGS. 1and 2, which illustrate the etching of a cavity underneath a porouslayer to produce an unsupported SMM diaphragm.

[0040]FIG. 4 shows a section corresponding to the preceding figures of afurther embodiment of an SMM diaphragm structure.

[0041]FIGS. 5a to 5 d show four embodiments of an SMM diaphragmstructure in a schematic top view.

[0042]FIG. 6 shows a schematic section of some sections of an SMMdiaphragm structure, illustrating the operation of an additional supportstructure.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0043]FIG. 1 shows a schematic section of a silicon substrate 1, inwhich a cavity 2 is formed. A porous diaphragm layer 3, delimitedlaterally by a masking layer 4, is situated over the cavity. FIG. 1 alsoshows an additional optional masking layer 5 which is situated onmasking layer 4, protecting it. A metal plating or an insulator may alsobe used as an optional masking layer.

[0044] Depending on the process, diaphragm layer 3 may be manufacturedof n-doped or p-doped silicon. Cavity 2 is preferably formed on thebasis of silicon having a different p-type doping. Bulk silicon orsilicon having a different p-type doping may be used as a siliconsubstrate material. n-doped silicon is preferably used for a maskinglayer 4 which delimits porous diaphragm layer 3.

[0045] The structure according to FIG. 2 differs from that of FIG. 1 bythe fact that an n-doped masking layer 6, which extends in depth overthe thickness of diaphragm layer 3 and over cavity 7, is formed in thesilicon substrate material. This only modifies insignificantly theetching surface over the depth when the cavity is produced, whichconsiderably simplifies the process control during manufacture.

[0046]FIGS. 3a and 3 b show the formation of a diaphragm layer 10together with cavity 11 underneath it for the case where thesemiconductor material has different doping regions in the lateraldirection when porous diaphragm layer 10 is produced. When poroussilicon is produced, this results in larger pores being produced incentral region 12 of the diaphragm in the present example than in edgeregion 13 of the diaphragm. In addition, the porosity of layer 10 islower in the edge region of the diaphragm due to appropriate processcontrol, which makes it possible to grow a proper epitaxial envelopinglayer when an SMM pressure sensor is manufactured, for example, in afurther process step.

[0047]FIG. 3a shows the condition when diaphragm layer 10 having adifferent porosity has just been produced together with suitable masking4, 5. During the subsequent production of cavity 11, as shown in FIG.3b, the macroporous structure of the center of the diaphragm favors goodpermeability for the gas formed when etching the cavity. This preventsaccumulation of gas underneath the diaphragm, which could be destroyedas early as during the production of cavity 11. Microporosity of porousdiaphragm layer 10, which is needed for good epitaxial growth in theedge region, is still ensured.

[0048]FIG. 4 shows one embodiment of an SMM diaphragm 20, which isformed in a silicon substrate 21 over a cavity 22; unlike the diaphragmlayers described previously, this diaphragm has a non-porous region 24within a porous region 25 in the center. This non-porous region 24corresponds to n-doped masking regions 23 for the lateral delimitationof the porous diaphragm and it is higher in the perpendicular directionto its lateral extension than thickness 26 of porous region 25.

[0049] As a result, when diaphragm 20 is deflected, its porous regions24, which are very sensitive, never touch bottom 27 of cavity 22.

[0050] Non-porous region 24 represents a stop which comes to rest oncavity bottom 27 in the event of overload, limiting the deflection.

[0051]FIG. 5a is a schematic top view of a diaphragm 20 of such adesign.

[0052]FIG. 5b differs from FIG. 5a by the fact that, in addition tonon-porous region 24 directly in the center of the diaphragm, anadditional non-porous annular region 28 is formed concentrically to thecenter of otherwise round porous regions 25.

[0053] The advantage of such an annular structure 28 is illustrated inFIG. 6 by a schematic section and arrows 31 through 35. When exposed topressure, which means an overload for porous diaphragm 20 and which issymbolized by large arrow 31, diaphragm 20 is pressed toward cavitybottom 27, which may result in rupture of diaphragm 20 in region 29 ofattachment. However, due to annular structure 28, the force is deflected(see arrow 33) in such a way that the load on the diaphragm isalleviated upward in the region of attachment (see arrow 34), althoughthere is a force acting downward (arrow 32). All in all, stress ruptureof diaphragm 20 in region of attachment 29 is prevented.

[0054] Other options of forming non-porous regions 40, 41 within porousregion 35 are illustrated in the top views of FIGS. 5c and 5 d. Inparticular, a grid structure 41, as shown in FIG. 5d, considerablyincreases the stability of the porous diaphragm both duringmanufacturing and in use.

1-21. (canceled).
 22. A method for manufacturing a diaphragm sensor having a semiconductor substrate in which a porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form an unsupported structure, the method comprising: doping the semiconductor substrate in a region of the diaphragm layer, the region of the diaphragm layer receiving doping that is different from that of a region of what is to become the cavity; processing semiconductor material of the region of the diaphragm layer so that it becomes porous; and removing or partially removing and rearranging semiconductor material underneath the porous semiconductor material to form the cavity.
 23. The method as recited in claim 22, wherein, in the region of the porous diaphragm layer, the semiconductor substrate receives doping which varies in at least one of a lateral and vertical direction.
 24. The method as recited in claim 22, wherein the doping of the semiconductor material for an edge region and a central region of the porous diaphragm layer is selected in such a way that mesopores are formed in the edge region and one of macropores or mesopores, having a higher porosity compared to the edge region, are formed in the central region.
 25. The method as recited in claim 22, wherein the semiconductor substrate receives different dopings in the region of the porous diaphragm layer and in the region of what is to become the cavity in such a way that mesopores are produced in the region of the porous diaphragm layer and nanopores having a comparatively higher porosity are produced in the region of what is to become the cavity, and wherein the method further comprises: removing or partially removing and rearranging the region having the nanopores.
 26. The method as recited in claim 25, wherein the region having the nanopores is first oxidized and subsequently the oxidized region is removed by etching.
 27. The method as recited in claim 22, wherein macropores or mesopores are produced in the region of the diaphragm layer, and the cavity is formed by electrolytic polishing underneath the region of the diaphragm layer.
 28. The method as recited in claim 22 wherein the processing step includes etching the semiconductor material in the region of the diaphragm layer, and wherein the method further comprises: illuminating a back of the semiconductor substrate to adjust a current density in etching the semiconductor material to produce the porous diaphragm region.
 29. The method as recited in claim 22, the processing step includes etching the semiconductor material in the region of the diaphragm layer, and the remaining step includes etching the semiconductor material in the region underneath the porous semiconductor material during electrolytic polishing to produce the cavity and wherein the method further comprises: illuminating a back of the semiconductor substrate to adjust a current density in etching the semiconductor material.
 30. The method as recited in claim 22, wherein the processing step includes etching the semiconductor material of the region of the diaphragm layer and etching the region that is to become the cavity, and wherein a porosity of approximately 10% to 30% is produced in the semiconductor material in the diaphragm region and a porosity greater than 80% in the region that is to become the cavity region by at least use of adjusting a current density and modifying an etching medium.
 31. A semiconductor component, comprising: a substrate made of semiconductor material including a diaphragm and a cavity located underneath the diaphragm for forming a semiconductor component structure, the diaphragm including a porous layer of semiconductor material wherein a degree of porosity of the layer varies in at least one of a lateral and a vertical direction.
 32. The semiconductor component as recited in claim 31, wherein the semiconductor component is a diaphragm sensor.
 33. The semiconductor component as recited in claim 31, wherein a porosity of the layer in an edge region of the diaphragm is lower than in a central region of the diaphragm.
 34. A semiconductor component as recited in claim 31, wherein a pore size in the porous layer varies in at least one of the lateral and vertical direction.
 35. The semiconductor component as recited in claim 31, wherein a pore size in the layer is lower in an edge region of the diaphragm than in a central region of the diaphragm.
 36. The semiconductor component as recited in claim 31, wherein in an edge region of the diaphragm, the layer is mesoporous.
 37. The semiconductor component as recited in claim 31, wherein in a central region of the diaphragm, the layer is mesoporous or macroporous.
 38. The semiconductor component as recited in claim 31, wherein the porous layer has macropores throughout.
 39. The semiconductor component as recited in claim 31, wherein the layer includes at least one region of non-porous semiconductor material, whose thickness is greater than a thickness of a region of the diaphragm.
 40. The semiconductor component as recited in claim 39, wherein the region of non-porous semiconductor material has an insular design.
 41. The semiconductor component as recited in claim 31, wherein a non-porous region is situated in a center of symmetry of the porous diaphragm layer.
 42. The semiconductor component as recited in claim 31, wherein the layer includes a non-porous region, the non-porous region having an annular shape.
 43. The semiconductor component as recited in claim 31, wherein an edge region of the porous layer includes a non-porous region of semiconductor material, which is used as a masking layer in etching and has a thickness which is greater than a thickness of the porous layer including a depth of the cavity.
 44. The semiconductor component as recited in claim 43, wherein the non-porous region fully surrounds the diaphragm. 